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Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 11. SCFG (Read/Write)
BIT NAME
X
DATA BIT
D15–D12
RESET STATE
X
Don’t care.
FUNCTION
Channel 2 load DAC. Set to 1 to load the new value of V DAC2(CODE) ,
upon completion of a V DAC2(CODE) calculation, into both the channel 2
DAC input and output registers. When set to 1, BUSY pulses high after a
LDAC2
D11
0
new V DAC2 output is calculated. Set to 0 to load the new value of
V DAC2(CODE) , upon completion of a V DAC2(CODE) calculation, to only the
channel 2 DAC input register. When set to 0, set the DACCH2 bit high in
the software load DAC register to transfer the V DAC(CODE) calculation
value from the DAC input register to the DAC output.
T2COMP1
T2COMP0
KSRC2-2
KSRC2-1
KSRC2-0
D10
D9
D8
D7
D6
0
0
0
0
0
Channel 2 temperature LUT control bits.
Channel 2 KLUT control bits.
Channel 1 load DAC. Set to 1 to load the new value of V DAC1 , upon
completion of a V DAC1(CODE) calculation, into both the channel 1 DAC
input and output registers. When set to 1, BUSY pulses high after a new
LDAC1
D5
0
V DAC1 output is calculated. Set to 0 to load the new value of V DAC1 ,
upon completion of a V DAC1(CODE) calculation, to only the channel 1
DAC input register. When set to 0, set the DACCH1 bit high in the
software load DAC register to transfer the V DAC(CODE) calculation value
from the DAC input register to the DAC output.
T1COMP1
T1COMP0
KSRC1-2
KSRC1-1
KSRC1-0
D4
D3
D2
D1
D0
0
0
0
0
0
Channel 1 temperature LUT control bits.
Channel 1 KLUT control bits.
38
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